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features q synchronous and asynchronous operation q synchronous 5-8 bit characters; internal or external character synchronization; automatic synchronization insertion q asynchronous 5-8 bit characters; clock rate - 1, 16, or 64 times baud rate; break character generation; 1, 1.5, or 2 stop bits; false start bit detection; automatic break detect and handling q synchronous baud rate - 1 to 64k baud q asynchronous baud rate - 1 to 19.2k baud q full-duplex, double-buffered transmitter and receiver q error detection - parity, overrun and framing errors q radiation-hardened process and design; total dose iradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) - sel let threshold: greater than 120mev-cm 2 /mg - neutron fluence: 3.0e14n/cm 2 q packaging options: - 36-lead flatpack - 68-lead flatpack q 5.0 and 3.3 volt operation q standard microcircuit drawing 5962-00505 - qml q and v compliant part q available as core ip for asic applications introduction the ut82crh51a is an enhanced version of the industry standard, universal synchronous/asynchronous receiver transmitter (usart), designed to provide data communications between subsystem. the ut82crh51a usart is built using utmc?s commercial radhard tm epitaxial cmos technology and is ideal for space applications. in a communication environment an interface device converts parallel format system data into serial format for transmission, and converts incoming serial format data into parallel system data for reception. the ut82crh51a is used as a peripheral device and is programmed by a host cpu to operate using virtually any serial data transmission technique. the usart accepts data characters from the cpu in a parallel format and then converts the data into a continuous serial data stream for transmission. simultaneously, the ut82crh51a receives serial data streams and converts the data into a parallel data character for the host cpu. the usart signals the cpu whenever it accepts a new character for transmission or whenever it has received a character for the cpu. the cpu reads the complete status of the usart at any time. these include data transmission errors and control signals such as syndet/brkdet, txempty. figure 1. ut82crh51a usart block diagram d(7:0) data bus buffer read/write control logic modem control transmit buffer (p-s) transmitter control receive buffer (s-p) receiver control reset clk c/ d rd wr cs dsr dtr cts rts txrdy txempty txc txd rxd rxrdy rxc syndet/ brkdet internal data bus standard products ut82crh51a usart preliminary data sheet december 9, 1999
2 1.0 functional description the ut82crh51a is designed for a wide range of microcomputers. like other i/o devices in a microcomputer system, its functional configuration is programmed by the system?s software for maximum flexibility. the ut82crh51a can support most serial data techniques in use. in a communication environment an interface device must convert parallel format system data into serial format for transmission and convert incoming serial format data into parallel system data for reception. the interface device must also delete or insert bits or characters that are functionally unique to the communication technique. therefore, the interface should appear "transparent" to the cpu, a simple input or output of byte- oriented system data (figure 7). 1.1 data bus buffer this three-state, bidirectional, 8-bit buffer is used to interface the ut82crh51a to the system data bus. data is transmitted or received by the buffer upon execution of input or output instructions of the cpu. control words, command words and status information are also transferred through the data bus buffer. the command status, data-in and data-out registers are separate, 8-bit registers communicating with the system bus through the data bus buffer. this functional block accepts inputs from the system control bus and generates control signals for overall device operation. it contains the control word register and command word register that store the various control formats for the device functional definition. 1.2 read/write control logic 1.2.1 reset (reset) a "high" on this input forces the ut82crh51a into an "idle" mode. the device remains at "idle" until a new set of control words is written into the ut82crh51a to program its function- al definition. minimum reset pulse width is 6t cy (clock must be running). a command reset operation also puts the device into the "idle" state. 1.2.2 clk (clock) the clk input is used to generate internal device timing and is normally connected to the phase 2 (ttl) output of the clock generator. no external inputs or outputs are referenced to clk, but the frequency of clk must be greater than 30 times the re- ceiver or transmitter data bit rates. 1.2.3 wr (write) a "low" on this input informs the ut82crh51a the cpu is writing data or control words to the ut82crh51a (figure 4). 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 figure 2. ut82crh51a pinout (36) v ss v dd d2 d1 d0 rxc dtr rts dsr reset clk txd txempty cts syndet txrdy v dd v ss v ss v dd rxd d4 nc nc d5 d6 d7 txc wr cs c/ d rd rxrdy d3 v dd v ss 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 top view nc nc v ss nc rxd nc d3 nc d2 nc d1 nc d0 nc v dd nc nc nc nc c/ d nc rd nc rxdy nc txrdy nc syndet nc cts nc txe nc nc n c n c d 4 n c d 5 n c d 6 n c d 7 n c t x c n c w r n c c s n c n c n c n c t x d n c c l k n c r e s e t n c d s r n c r t s n c d t r n c r x c n c n c figure 3. ut82crh51a pinout (68)
3 1.2.4 rd (read) a "low" on this input informs the ut82crh51a the cpu is reading data or status information from the ut82crh51a (fig- ure 4). 1.2.5 c/ d (control/data) this input, in conjunction with the wr and rd inputs, informs the ut82crh51a the word on the data bus is either a data character, control word or status information. 1 = control/status; 0 = data 1.2.6 cs (chip select) a "low" on this input selects the ut82crh51a. no reading or writing will occur unless the device is selected. when cs is high, the data bus is in the float state and rd and wr have no effect on the chip. 1.3 modem control the ut82crh51a has a set of control inputs and outputs that can be used to simplify the interface to almost any modem. the modem control signals are general purpose in nature and can be used to functions, other than modem control, if necessary (figure 5). 1.3.1 dsr (data set ready) the dsr input signal is a general-purpose, 1-bit inverting input port. its condition can be tested by the cpu using a status read operation. the dsr input is normally used to test modem con- ditions such as data set ready. 1.3.2 dtr (data terminal ready) the dtr output signal is a general-purpose, 1-bit inverting out- put port. it can be set "low" by programming the appropriate bit in the command instruction word. the dtr output signal is normally used for modem control such as data terminal ready. 1.3.3 rts (request to send) the rts output signal is a general-purpose, 1-bit inverting out- put port. it can be set "low" by programming the appropriate bit in the command instruction word. the rts output signal is normally used for modem control such as request to send. 1.3.4 cts (clear to send) a "low" on this input enables the ut82crh51a to transmit se- rial data if the txenable bit in the command byte is set to a "one". if either a txenable off or cts off condition occurs while the tx is in operation, the tx transmits all the data in the usart written prior to txdisable command before shutting down. 1.4 transmit buffer the transmit buffer accepts parallel data from the data bus buffer, converts it to a serial bit stream, inserts the appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of data on the txd output pin on the falling edge of txc . the transmitter begins transmission upon being enabled if cts = 0. the txd line will be held in the marking state immediately upon a master reset or when txen- able or cts is off or the transmitter is empty (figure 5). 1.5.transmitter control the transmitter control manages all activities associated with the transmission of serial data. it accepts and issues signals both externally and internally to accomplish this function (figure 5). 1.5.1 txrdy (transmitter ready) this output signals the cpu the transmitter is ready to accept a data character. the txrdy output pin can be used as an inter- rupt to the system since it is masked by txenable; or, for polled operation, the cpu can check txrdy using a status read op- eration. txrdy is automatically reset by the leading edge of wr when a data character is loaded from the cpu. note: when using the polled operation, the txrdy status bit is not masked by txenable, but will only indicate the empty/ full status of the tx data input register. 1.5.2 txempty (transmitter empty) when the ut82crh51a has no characters to send, the txemp- ty output will go "high". it resets upon receiving a character c/ d rd wr cs 0 0 1 0 data -> data bus 0 1 0 0 data bus -> data 1 0 1 0 status -> data bus 1 1 0 0 data bus -> control x 1 1 0 data bus -> 3-state x x x 1 data bus -> 3-state figure 4. ut82crh51a block diagram showing data bus buffer and read/write logic functions d(7:0) data bus buffer read/write control logic modem control transmit buffer (p-s) trans- mitter control receive buffer (s-p) receiver control reset clk c/ d rd wr cs dsr dtr cts rts txrdy txempty txc txd rxd rxrdy rxc syndet/ brkdet
4 from the cpu if the transmitter is enabled. txempty remains low when the transmitter is disabled even if it is actually empty. txempty can be used to indicate the end of a transmission mode, so the cpu knows when to turn the line around in the half-duplex operational mode. in the synchronous mode, a "high" on this output indicates that a character has not been loaded and the sync character or char- acters are about to be or are being transmitted automatically as "fillers". txempty does not go low when the sync charac- ters are being shifted out. 1.5.3 txc (transmitter clock) the transmitter clock controls the rate at which the character is to be transmitted. in the synchronous transmission mode, the baud rate (1x) is equal to the txc frequency. in asynchronous transmission mode, the baud rate is a fraction of the actual txc frequency. a portion of the mode instruction selects this factor; it can be 1, 1/16 or 1/64 the txc. for example: if baud rate equals 110 baud, txc equals 110 hz in the 1x mode txc equals 1.72 khz in the 16x mode txc equals 7.04 khz in the 64x mode the falling edge of txc shifts the serial data out of the ut82crh51a. 1.6 receive buffer the receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique and sends an "assembled" charac- ter to the cpu. serial data is input to rxd pin, and is clocked in on the rising edge of rxc (figure 6). 1.7 receiver control this functional block manages all receiver-related activities which consists of the following features (figure 6). ? the rxd initialization circuit prevents the ut82crh51a from mistaking an unused input line for an active low data line in the "break condition". before starting to receive serial characters on the rxd line, a valid "1" must first be detected after a chip master reset. once this has been determined, a search for a valid low (start bit) is enabled. this feature is only active in the asynchronous mode, and is only done once for each mas- ter reset. ? the false start bit detection circuit prevents false starts due to a transient noise spike by first detecting the falling edge and then strobing the nominal center of the start bit (rxd = low). ? parity error detection sets the corresponding status bit. ? the framing error status bit is set if the stop bit is absent at the end of the data byte (asynchronous mode). 1.7.1 rxrdy (receiver ready) this output indicates the ut82crh51a contains a character ready to be input to the cpu. rxrdy can be connected to the interrupt structure of the cpu or, for polled operation, the cpu checks the condition of rxrdy using a status read operation. rxenable, when off, holds rxrdy in the reset condition. for asynchronous mode, to set rxrdy, the receiver must be en- abled to sense a start bit and a complete character must be as- sembled and transferred to the data output register. for synchronous mode, to set rxrdy, the receiver must be en- abled and a character must finish assembly and be transferred to the data output register. failure to read the received character from the rx data output register prior to the assembly of the next rx data character will set overrun condition error and the previous character will be written over and lost. if the rx data is being read by the cpu when the internal transfer is occurring, overrun error will be set and the old character will be lost. 1.7.2 rxc (receiver clock) the receiver clock controls the rate at which the character is to be received. in synchronous mode, the baud rate (1x) is equal to the actual frequency of rxc . in asynchronous mode, the baud rate is a fraction of the actual rxc frequency. a portion of the mode instruction selects this factor: 1, 1/16 or 1/64 the rxc . for example: baud rate equals 300 baud, if rxc equals 300 hz in the 1x mode rxc equals 4800 hz in the 16x mode rxc equals 19.2 khz in the 64x mode baude rate equals 2400 baude, if rxc equals 2400 hz in the 1x mode rxc equals 38.4 khz in the 16x mode rxc equals 153.6 khz in the 64x mode data is sampled into the ut82crh51a on the rising edge of figure 5. ut82crh51a block diagram showing modem and transmitter buffer and control functions d(7:0) data bus buffer read/write control logic modem control transmit buffer (p-s) trans- mitter control receiver buffer (s-p) receiver control reset clk c/ d rd wr cs dsr dtr cts rts txrdy txempty txc txd rxd rxrdy rxc syndet/ brkdet internal data bus
5 rxc . note: in most communications systems, the ut82crh51a handles both the transmission and reception operations of a sin- gle link. consequently, the receive and transmit baud rates will be the same. both txc and rxc requires identical frequen- cies for this operation and can be tied together and connected to a single frequency source (baud rate generator) to simplify the interface. 1.7.3 syndet (sync detect/brkdet break detect) this pin is used in synchronous mode for syndet and may be used as either input or output programmable through the control word. it is reset to output mode low upon reset. when used as an output (internal sync mode), the syndet pin goes high to indicate that the ut82crh51a has located the sync char- acter in the receive mode. if the ut82crh51a is programmed to use double sync characters (bisync), then syndet goes high in the middle of the last bit of the second sync character. syn- det automatically resets upon a status read operation. when used as an input (external sync detect mode), a positive going signal causes the ut82crh51a to start assembling data characters on the rising edge of the next rxc . once in sync, the "high" input signal can be removed. when external sync detect is programmed, internal sync detect is disabled. 1.7.4 break (async mode only) this output goes high whenever the receiver remains low through two consecutive stop bit sequences (including the start bits, data bits, and parity bits). break detect may also be read as a status bit. it is reset only upon a master chip reset or rx data returning to a "one" state. figure 6. ut82crh51a block diagram showing receiver buffer and control functions d(7:0) data bus buffer read/write control logic modem control transmit buffer (p-s) trans- mitter control receiver buffer (s-p) receiver control reset clk c/ d rd wr cs dsr dtr cts rts txrdy txempty txc txd rxd rxrdy rxc syndet/ brkdet internal data bus control bus address bus data bus ut82crh51a c/ d cs d 7 -d 0 rd wr clk reset a 0 i/o r i/o w reset 0 2 (ttl) 8 figure 7. ut82crh51a interface to standard system bus
6 2.0 detailed operation description 2.1 general the complete functional definition of the ut82crh51a is pro- grammed by the system?s software. a set of control words must be sent out by the cpu to initialize the ut82crh51a to sup- port the desired communications format. these control words will program the: baud rate, character length, number of stop bits, synchronous or asyn- chronous operation, even/odd/off parity, etc. in the synchronous mode, options are also provided to select ei- ther internal or external character synchronization (figure 8). once programmed, the ut82crh51a is ready to perform its communication functions. the txrdy output is raised "high" to signal the cpu the ut82crh51a is ready to receive a data character from the cpu. this output (txrdy) is reset automat- ically when the cpu writes a character into the ut82crh51a. on the other hand, the ut82crh51a receives serial data from the modem or i/o device. upon receiving an entire character, the rxrdy output is raised "high" to signal the cpu the ut82crh51a has completed character ready for the cpu to fetch. rxrdy is reset automatically upon the cpu data read operation. the ut82crh51a cannot begin transmission until the txen- able (transmitter enable) bit is set in the command instruction and it has received a clear to send ( cts ) input. the txd output is held in the marking state upon reset. 2.2 programming the ut82crh51a prior to starting data transmission or reception, the ut82crh51a must be loaded with a set of control words gen- erated by the cpu. these control signals define the complete functional definition of the ut82crh51a and must immediate- ly follow a reset operation (internal or external). the control words are split into two formats: 1. mode instruction 2. command instruction 2.2.1 mode instruction this instruction defines the general operational characteristics of the ut82crh51a. it must follow a reset operation (internal or external), once the mode instruction has been written into the ut92crh51a by the cpu, sync characters or command in- structions (figure 8). 2.2.2 command instruction this instruction defines a word that is used to control the actual operation of the ut82crh51a. both the mode and command instructions must conform to a specified sequence for proper device operation (see figure 8). the mode instruction must be written immediately following a reset operation prior to using the ut82crh51a for data com- munication. all control words written into the ut82crh51a after the mode instruction loads the command instruction. command instruc- tions can be written into the ut82crh51a at any time in the data block during the operation of the ut82crh51a. to return to the mode instruction format, the master reset bit in the com- mand instruction word can be set to initiate an internal reset op- eration which automatically places the ut82crh51a back into the mode instruction format. command instructions must fol- low the mode instructions or sync characters. 2.2.3 mode instruction definition the ut82crh51a can be used for either asynchronous or synchronous data communication. to understand how the mode instruction defines the functional operation of the ut82crh51a, the designer views the device as two separate components, one asynchronous and the other synchronous, sharing the same package. the format definition can be changed only after a master chip reset. for explanation purpos- es the two formats will be isolated. note: when parity is enabled it is not considered as one of the data bits for the purpose of programming the word length. the actual parity bit received on the rx data line cannot be read on the data bus. in the case of a programmed character length of less than 8 bits, the least significant data bus bits holds the data; unused bits are "don?t care" when writing data to the ut82crh51a and will be "zeroes" when reading the data from the ut82crh51a. 2.2.4 asynchronous mode (transmission) whenever a data character is sent by the cpu the ut82crh51a automatically adds a start bit (low level) fol- lowed by the data bits (least significant bit first), and the pro- grammed number of stop bits to each character. also, an even or odd parity bit is inserted prior to the stop bit(s) as defined by mode instruction sync character 1 sync character 2 command instruction data data command instruction command instruction c/ d = 1 c/ d = 1 c/ d = 1 c/ d = 1 c/ d = 0 c/ d = 1 c/ d = 0 c/ d = 1 sync mode only* note: the second sync character is skipped if mode instruction has programmed the ut82crh51a to single character internal sync mode. both sync characters are skipped if mode instruction has programmed the ut82crh51a to async mode or external sync mode. figure 8. typical data block
7 the mode instruction. the character is then transmitted as a se- rial data stream on the txd output. the serial data is shifted out on the falling edge of txc at a rate equal to 1, 1/16, or 1/64 that of the txc as defined by the mode instruction. break char- acters can be continuously sent to the txd if commanded to do so. when no data characters have been loaded into the ut82crh51a the txd output remains "high" (marking) unless a break (continuously low) has been programmed (figure 9). 2.2.5 asynchronous mode (receive) the rxd line is normally high. a falling edge on this line trig- gers the beginning of a start bit. the validity of this start bit is checked by again strobing this bit at its nominal center (16x or 64x mode only). if a low is detected again, it is a valid start bit, and the bit counter starts counting. the bit counter thus locates the center of the data bits, the parity bit (if it exists), and the stop bits. if parity error occurs, the parity error flag is set. data and parity bits are sampled on the rxd pin with the rising edge of rxc . if a low level is detected as the stop bit, the framing error flag sets. the stop bit signals the end of a character. note: the receiver requires only one stop bit regard- less of the number of stop bits programmed. this character is then loaded into the parallel i/o buffer of the ut82crh51a. the rxrdy pin is raised to signal the cpu that a character is ready to be fetched. if a previous character has not been fetched by the cpu, the present character replaces it in the i/o buffer, and the overrun error flag is raised (thus the previous char- acter is lost). all of the error flags can be reset by an error reset instruction. the occurrence of any of these errors will not affect the operation of the ut82crh51a (figure 10). 2.2.6 synchronous mode (transmission) the txd output is continuously high until the cpu sends its first character to the ut82crh51a which usually is a sync character. when the cts line goes low, the first character is se- rially transmitted out. all characters are shifted out on the fall- ing edge of txc . data is shifted out at the same rate as the txc . once transmission has started, the data stream at txd output continues at the txc rate. if the cpu does not provide the ut82crh51a with a data character before the ut82crh51a transmitter buffers become empty, the sync characters (or character if in single sync character mode) will be automati- cally inserted in the txd data stream. in this case, the txemp- ty pin is raised high to signal that the ut82crh51a is empty and sync characters are being sent out. txempty does not go low when the sync is being shifted out (see figure 11). the txempty pin is internally reset by a data character being writ- ten into the ut82crh51a. s 2 s 1 ep pen l 2 l 1 b 2 b 1 d 5 d 6 d 7 d 4 d 3 d 2 d 1 d 0 0 sync mode 0 1 (1x) 0 0 (16x) 1 1 1 (64x) baud rate factor 0 5 bits 0 1 6 bits 0 0 7 bits 1 1 1 8 bits character length parity enable 1 = enable 0 = disable even parity generation/check 1 = even 0= odd 0 invalid 0 1 1 bits 0 0 1 1/2 bits 1 1 1 2 bits number of stop bits (only affects tx:rx never requires more than one stop bit) figure 9. mode and command instruction format, asynchronous node s 2 s 1 ep pen l 2 l 1 b 2 b 1 d 5 d 6 d 7 d 4 d 3 d 2 d 1 d 0 0 sync mode 0 1 (1x) 0 0 (16x) 1 1 1 (64x) baud rate factor 0 5 bits 0 1 6 bits 0 0 7 bits 1 1 1 8 bits character length parity enable 1 = enable 0 = disable 0 invalid 0 1 1 bits 0 0 1 1/2 bits 1 1 1 2 bits number of stop bits figure 11. synchronous mode data data sync 1 sync 2 data - - - - - - txd automatically inserted by usart txempty nominal center of last bit falls upon cpu writing a character to the usart
8 2.2.7 synchronous mode (receive) in this mode, character synchronization can be internally or ex- ternally achieved. if the sync mode has been programmed, an enter hunt command should be included in the first com- mand instruction word written. data on the rxd pin is then sampled on the rising edge of rxc . the content of the rx buffer is compared at every bit boundary with the first sync character until a match occurs. if the ut82crh51a has been pro- grammed for two sync characters, the subsequent received character is also compared; when both sync characters have been detected, the usart ends the hunt mode and is in char- acter synchronization. the syndet pin is then set high and is reset automatically by a status read. if parity is pro- grammed, syndet will not be set until the middle of the parity bit instead of the middle of the last data bit. in the external sync mode, synchronization is achieved by ap- plying a high level of the syndet pin, thus forcing the ut82crh51a out of the hunt mode. the high level can be removed after one rxc cycle. an enter hunt command has no effect in the asynchronous mode of operation. parity error and overrun error are both checked in the same way as in the asynchronous rx mode. parity is checked when not in hunt, regardless of whether the receiver is enabled or not (figure 12). the cpu can command the receiver to enter the hunt mode if synchronization is lost. this will also set all the used character bits in the buffer to a "one", thus preventing a possible false syndet caused by data that happens to be in the rx buffer at enter hunt time. note: the syndet f/f is reset at each status read regardless of whether internal or external sync has been programmed. this does not cause the ut82crh51a to return to the hunt mode. when the sync mode but not in hunt, sync detection is still functional, but only occurs at the "known" word boundaries. thus, if one status read indicates syndet and a second status read also indicates syndet, then the programmed syndet characters have been received since the previous status read. (if double character sync has been programmed, then both sync characters have been contig- uously received to gate a syndet indication.) when external syndet mode is selected, internal sync detection is disabled, and the syndet f/f may be set at any bit boundary (figure 13). transmitter output start bit data bits parity bits stop bits d 0 d 1 --------------d x generated by ut82crh51a marking txd receiver input start bit data bits parity bits stop bits d 0 d 1 --------------d x does not appear on the data bus rxd programmed character length transmission format data character cpu byte (5-8 bits/char) start bit data character parity bits stop bits assembled serial data output (txd) start bit data character parity bits stop bits serial data input (rxd) receive format data character cpu byte (5-8 bits/char) *note: if character length is defined as 5,6 or 7 bits, the unused bits are set to "zero" figure 10. asynchronous mode }
9 3.0 command instruction definition once the functional definition of the ut82crh51a has been programmed by the mode instruction and the sync characters are loaded (if in sync mode) then the device is ready to be used for data communication. the command instruction controls the actual operation of the selected format. functions such as en- able transmit/receive, error reset and modem controls are provided by the command instruction. once the mode instruction has been written into the ut82crh51a and the sync characters inserted, if necessary, then all further "control write" (c/d = 1) will load a command instruction. a reset operation (internal or external) returns the ut82crh51a to the mode instruction format. note: internal reset on power-up when power is first applied, the ut82crh51a may come up in the mode, sync character or command format. to guarantee that the device is in the command instruction format before the reset command is issued, it is safest to execute the worst-case initialization sequence (sync mode with two sync characters). loading three 00hs consecutively into the device with c/ d = 1 configures sync operation and writes two dummy 00h sync characters. an internal reset command (40h) may then be is- sued to return the device to the "idle" state (figure 14). d 5 d 6 d 4 d 3 d 2 d 1 d 0 0 5 bit 0 1 6 bits 0 0 7 bits 1 1 1 8 bits character length parity enable 1 = enable 0 = disable even parity generation/check 1 = even 0= odd external sync detect 1 = syndet is an input 0 = syndet is an output scs es d ep pe n l 2 l 1 0 0 d 7 figure 12. mode instruction format, synchronous mode single character sync 1 = syngle sync character 0 = double sync character data character cpu byte (5-8 bits/char) sync char 2 data character assembled serial data output (txd) sync char 1 receive format data character cpu byte (5-8 bits/char) sync char 2 data character assembled serial data output (rxd) sync char 1 figure 13. data format, synchronous mode d 5 d 6 d 4 d 3 d 2 d 1 d 0 transmit enable 1 = enable 0 = disable data terminal ready "high" will force dtr out- put to zero receive enable 1 = enable 0 = disable send break character 1 = forces txd "low" 0 = normal operation eh ir rts er sbr rxe dt txe d 7 figure 14. mode instruction format, synchronous mode error reset 1 = reset error flags pe, oe, fe request to send "high" will for rts output to zero internal reset "high" returns ut82crh51a to mode instruction format enter hunt mode 1 = enable search for sync characters note: error reset must be performed whenever rxenable and enter hunt are programmed.
10 4.0 status read definition in data communication systems it is often necessary to examine the "status" of the active device to ascertain if errors have oc- curred or other conditions requiring the processor?s attention. the ut82crh51a has facilities that allow the programmer to "read" the status of the device at any time during the functional operation. (status update is inhibited during status read.) a normal "read" command is issued by the cpu with c/ d = 1 to accomplish this function. some of the bits in the status read format have identical mean- ings to external output pins to that the ut82crh51a can be used in a completely polled or interrupt-driven environment. txrdy is an exception (figure 15). note: status update can have a maximum delay of 28 clock pe- riods from the actual event affecting the status. d 5 d 6 d 4 d 3 d 2 d 1 d 0 parity error the pe flag is set when a parity error is detected. it is reset by the er bit of the command instruction. pe does not inhibit operation of the ut82crh51a overrun error the oe flag is set when the cpu does not read a character before the next one becomes available. it is re- set by the er bit of the command instruction. oe does not inhibit op- eration of the ut82crh51a how- ever, the previously overrun character is lost. framing error (async only) the fe flag is set when a valid stop bit is not detected at the end of every character. it is reset by the er bit of the command instruction. fe does not inhibit the operation of the ut82crh51a dsr syn- det/ fe oe pe tx- emp- rxr dy txrd y d 7 note 1 same definition as i/o pins data set ready indicates that the dsr is at a zero level. note : txrdy status bit has different meanings from the txrdy output pin. the former is not conditioned by cts and txen; the latter is conditioned by both cts and txen. i.e txrdy status bit = db buffer empty txrdy pin out = db buffer empty + ( cts -0) + (txen-1) figure 15. status read format
11 5.0 applications of the ut82crh51a figures 16 thru 19 are examples of ut82crh51a application environments. control bus address bus data bus ut82crh51a 8 rxd txd rxc txc eia to ttl con- vert (opt) baud rate generator crt terminal figure 16. asynchronous serial interface to crt terminal, dc-9600 baud control bus address bus data bus ut82crh51a 8 rxd txd rxc txc synchronous terminal or peripheral device figure 17. synchronous interface to terminal, or peripheral device syndet
12 control bus address bus data bus u t 8 2 c r h 5 1 a 8 rxd txd dsr dtr b u s t r a n s c e i v e r figure 18. asynchronous interface to serial bus cts rts txc txc baud rate generator s e r i a l b u s control bus address bus data bus u t 8 2 c r h 5 1 a 8 rxd txd rxc txc b u s t r a n s c e i v e r figure 19. synchronous interface to serial bus syndet cts dsr dtr s e r i a l b u s rts
13 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. not tested, inherent of cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute maxim um rating conditions for extended periods may affect device reliability and performance. parameter limit units total dose 300 krad(si) sel latchup >120 mev-cm 2 /mg neutron fluence 2 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o voltage any pin -.5 to +7 v t stg storage temperature range -65 t o +150 c t j maximum junction temperature +175 c p d maximum power dissipation 1 w
14 6.0 dc electrical characteristics (pre/post-radiation)* v dd = 5.0v 10%; t a = -55 c to 125 c, gnd = 0v) notes: * post-radiation performance guaranteed at 25 c per mil-std-883. symbol parameter condition minimum maximum unit v il low-level input voltage -0.5 0.8 v v ih high-level input voltage 2.2 v cc v v ol low-level output voltage i ol = 2.2ma 0.45 v v oh high-level output voltage i oh = -400 m a 2.4 v i ofl output float leakage v out = v cc to 0.45v + 10 m a i il input leakage v in = v cc to 0.45v + 10 m a i cc power supply current all outputs = high 100 ma c in input capacitance fc = 1mhz 10 pf c i/o i/o capacitance unmeasured pins returned to gnd 20 pf
15 7.0 ac characteristics (post-radiation) (v dd = 5.0v 5%; t a = -55 c to 125 c, gnd = 0v) symbol parameter minimum maximum unit t cy clock period 1,2 200 - ns t clk clock high pulse width 100 - ns t clk clock low pulse width 100 ns t r , t f clock rise and fall time 20 ns t dtx txd delay from falling edge of txc 1 m s f t x transmitter input clock frequency 1x baud rate 16x baud rate 64x baud rate 1 1 1 64 310 615 khz t tpw transmitter input clock pulse width 1x baud rate 16x and 64x baud rate 12 1 t cy t tpd transmitter input clock pulse delay 1x baud rate 16x and 64x baud rate 15 3 t cy f rx receiver input clock frequency 1x baud rate 16x baude rate 64x baude rate 1 1 1 64 310 615 khz t rpw receiver input clock pulse width 1x baude rate 16x and 64x baude rate 12 1 t cy t rpd receiver input clock pulse width 1x baude rate 16x and 64x baude rate 15 3 t cy t txrdy txrdy pin delay from end o f last bit 3 35 n s t txrdy clear txrdy falling from leading edge of wr 3 50 ns t rxrdy rxrdy pin delay from center of last bit 3 26 t cy t rxrdy clear rxrdy falling from leading edge of rd 3 400 ns t is internal syndet delay from rising edge of rxc 3 26 t cy t es external syndet set-up time after rising edge of rxc 3 18 t cy t txempty 4 txempty delay from center of last bit 3 20 - t cy t wc 4 control delay from rising edge of write (txen, dtr , rts ) 3 8 - t cy t cr 4 control to read set-up time ( dsr , cts ) 3 20 - t cy
16 note: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 300 krad(si). 1. the txc and rxc frequencies have the following limitations with respect to clk: for 1x vaude rate, f tx or f rx < 1/(30 t cy ). for 16x and 64x baud rate, f tx or f rx < 1/(4.5 t cy ). 2. rest pulse width = 6 t cy minimum. system clock must be running during reset. 3. status update can have a maximum delay of 28 clock periods from the event affecting the status. 4. guaranteed by simulation, not tested. ac characteristics read cycle (post-radiation) 1 (v dd = 5.0v 5%; t a = -55 c to 125 c, gnd = 0v) note: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 300 krad(si). 1. ac timing measured v oh = 2.0, v ol = 0.8. 2. chip select (cs) and command/data (c/d) are considered as addresses. 3. assumes that address is valid beroe r ea d falling. 4. guaranteed by simulation, not tested. ac characteristics write cycle (post-radiation) 1 (v dd = 5.0v 5%; t a = -55 c to 125 c, gnd = 0v) note: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 300 krad(si). 1. ac timing measured v oh = 2.0, v ol = 0.8. 2. th is recovery time is for mode initialization only. write data is allowed only when txrdy = 1. recovery time between writes for asynchronous mode is 8 t cy and for synchronous mode is 16 t cy . 3. guaranteed by simulation, not tested. symbol parameter minimum maximum unit t ar 4 address stable before read ( cs , c/ d ) 2 0 - ns t ra 4 address hold time for read ( cs , c/ d ) 2 0 - ns t rr 4 read pulse width 2 0 - ns t rd data delay from read 3 c l = 150 pf - 30 ns t df read to data floating 1.8 45 ns symbol parameter minimum maximum unit t aw 3 address stable before write 0 - ns t wa 3 address hold time for write 0 - ns t ww 3 write pulse width 2 0 - ns t dw 3 data delay from write 15 - ns t wd 3 data hold time for write 5 - ns t r v 3 recovery time between writes 2 6 - t cy
17 t cy t clk t clk clock f t f t r figure 20. sys clock t dtx t dtx t tpd t tpw txc (1x mode) txc (16x mode) tx data figure 21. tx clock and data start bit data bit data bit 3t cy t clk 3t cy 16 rxc periods (16x mode) 8 rxc periods (16x mode) t rpd t rpw (rx baud counter starts here) rx data rxc (1x mode) rxc (16x mode) int sampling pulse figure 22. rx clock and data
18 don't care data valid don't care t wa t aw t wa t aw t wd t dw t ww t txrdy clear txrdy wr data in (d.b.) c/ d cs figure 23. cpu to usart wr data data float data out valid data float t ra t ar t ra t ar t df t rd t rr t rxrdy clear rxrdy rd data out (d.b.) c/ d cs figure 24. usart to cpu rd data
19 don't care data valid don't care t wa t aw t wa t aw t wd t dw t wc t ww dtr , rts 1 wr data in (d.b.) c/ d cs figure 25. wr control data float data out valid data float t ra t ar t ra t ar t df t rd t rr t cr dsr , cts 2 rd data out (d.b.) c/ d cs figure 26. rd control
20 cts txempty txready (status bit) txready (pin) c/ d wr txdata t txrdy wr data 4 wr data 3 wr data 2 wr data 1 wr txen wr sbrk t txempty 0 1 2 3 4 5 6 7 start bit stop bit data char 1 data char 2 data char 3 data char 4 example format = 7 bit character with parity & 2 stop bits figure 27. tx control-flags async t rxrdy break detect framing error overrun error rxrdy c/d wr rd rxdata (status bit) (status bit) data char 1 data char 2 data char 3 s t a r t b i t d a t a b i t 0 1 2 3 4 5 6 p a r i t y b i t s t o p b i t s t a r t b i t d a t a b i t 0 1 2 3 4 5 6 p a r i t y b i t s t o p b i t break rxen errres data char 2 lost wr err rst rd data wr rxen rxen example format = 7 bit character with parity and 2 stop bits figure 28. rx control-flags async
21 cts txempty txready txready c/ d wr txdata (pin) (status bit) 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 par par par par par par par marking data char 1 state data char 2 data char 3 data char 4 data char 5 sync char 1 sync char 2 sync char 1 marking state marking state spacing state etc. wr command sbrk wr command sbrk wr data char 5 wr data char 1 wr data char 2 wr data char 3 wr data char 4 example format = 5 bit character with parity and 2 sync characters figure 29. tx control-flags sync
22 data don't sync sync data data data sync sync syndet (pin) note 1 syndet (s.b) overrun error (s.b) rxready (pin) c/ d wr rd txdata rxc char 1 char 2 char 1 char 2 char 3 char 1 char 2 care char 1 x x x x x x x 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r 0 1 2 3 4 p a r x x x x x x x x etc. don't care data char 2 t is t es note 2 data char 2 lost wr eh rxen rd data char 1 rd data rd sync char 1 rd data char 3 rd status wr eh f rd status rd status wr err rst char assy begins exit hunt mode set sync det char assy begins exit hunt mode set syn det (status bit) set syn det (status bit) note 1: internal sync, 2 sync characters, 5 bits, with parity note 2: external sync, 5 bits, with parity figure 30. rx control-flags sync
23 top view d 1.000 0.025 e 0.700 0.015 l 0.330 min. b 0.016 0.002 e 0.050 pin 1 i.d. (geometry optional) a 0.130 max. q 0.070 0.010 (at ceramic body) end view c 0.007 +0.002 -0.001 packaging notes: 1. all package finishes are per mil-prf-38535. 2. it is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. a thermally conductive material such as mereco xln-589 or equivalent should be used. 3. letter designations are for cross-reference to mil-std-1835. figure 31. 36-pin ceramic flatpack
24 notes : 1. all exposed metalized area must be gold plated over nickel plating per mil - prf-38535. 2. lead finish is in accordance with mil-prf-38535. 3. lid is electrically connected to vss. 4. letter designations are to cross-reference to mil-std-1835. 5. lead true position tolerances and coplanrity are not measured. 6. dogleg geometries optional within dimensions shown. figure 32. 68-pin ceramic flatpack
ordering information ut82crh51a usart: ut 82crh51a * ** - * * * * * notes: 7. lead finish (a,c, or x) must be specified. 8. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). device type: ut82crh51a usart device type modifier: (c) = cmos-compatible i/o leve l access time: not applicable package type: ( 68w) = 68-lead quad flatpack (36w) = 36-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder)
26 ut82crh51a: smd 5962 - 00505 ** * * * notes: 1. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening federal stock class designator: no options total dose ( r) = 3e5 r ad(si ) drawing number: 5962-00505 device type 01 = ut82crh51a usart class designator: ( q) = qml class q (v) = qml class v case outline: (tbd) = 68-lead quad flatpack (tbd) = 36-lead flatpack (dual-in-line) lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder

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